Optimization Of Double Gate Junctionless Field Effect Transistor For Low powerMemory Application Using T-Cad Tools.

Abstract

This terminal report summarizes the completed project titled " Optimization Of Double Gate Junctionless Field Effect Transistor For Low power Memory Application Using T-Cad Tools.." The project aimed to develop a new structure for planar JLFETs that significantly decreases the off-state current. To achieve this goal, the project pursued specific objectives. Firstly, the length, thickness, and construction materials of the spacer, which is the distance between the source/drain and the gate, were varied to improve the on-current and reduce the off-state current of the JLFETs. Through extensive simulations and analysis, optimal spacer parameters were determined. Secondly, the project focused on reducing the action of the parasitic Bipolar Junction Transistor (BJT) by implementing high dielectric constant materials like hafnium dioxide between the channel and the ground plane. This implementation effectively minimized the unwanted current leakage, leading to improved device performance. Additionally, different semiconductor materials, such as germanium, were utilized to increase the on-current through the channel. This approach enhanced the overall performance of the JLFETs and contributed to achieving higher on-current. The project relied on the use of TCAD (Technology Computer-Aided Design) tools to simulate and optimize the proposed structure. Through rigorous simulations and analysis, the project yielded valuable insights into the optimization of double gate junctionless field-effect transistors. In conclusion, the project successfully developed an improved structure for planar JLFETs that effectively reduced the gate-induced leakage current. By achieving the specific objectives outlined above, the project significantly enhanced the performance and efficiency of JLFETs, contributing to advancements in semiconductor technology. The findings of this project can be utilized in the design and fabrication of future JLFET devices, enabling improved functionality and reduced power consumption.