Design and Optimization of Tunnel Field-Effect Transistor using Dielectric Engineering for Analog/RF Amplification

Abstract

This thesis presents the impact of dielectric pocket (dielectric engineering) on tunnel FET to mitigate the ambipolar current and improves the analog/RF performance of TFETs. It is observed that when a dielectric pocket is inserted into the drain region, it affects the channel drain junction, and then the increase of tunneling barrier of the interface. In this work, various metrics are invoked in simulation by varying different parameters at the dielectric pocket, such as the dielectric material of the pocket, pocket thickness, and length of the pocket. Furthermore, by replacing three dielectric materials at DP (i.e., HfO2, SiO2, and Si3N4), a high k dielectric material (HfO2) delivers a greater reduction in OFF-state current (7.88x10-19A/µm) and ambipolar current (1.22x10-17A/µm). Additionally, when comparing conventional TFETs with DP-TFETs (proposed study) for the negative gate voltages (i.e., ambipolar current), the value of IAMB is suppressed from 9.38×10-7A/µm to 1.22×10−17A/µm, thus the ambipolar current is reduced by ten (10) orders of magnitude without decreasing (affecting) ON-state current performance. However, the analog/RF parameter of DP-TFETs with low dielectric material (SiO2) is much better than that of high k dielectric (HfO2) and medium K dielectric material (Si3N4) and has a peak gm of 2.7×10−6 S/µm, a gain-bandwidth product of 0.3GHz, and a cut-off frequency of 0.23 GHz. All the simulations are done in the Atlas Module of the SILVACO TCAD tool. It is considered the Kane tunneling model in all the simulations. Finally, to show the practical applicability of the DP-TFETs, the inverter analysis of DP-TFET is investigated.