Design and Optimization of Junction-Less Nanowire Tunnel FET for Low-Power Analog Application

Abstract

Researchers worldwide are engaged in developing innovative approaches to achieve the objectives outlined in the International Technology Roadmap for Semiconductors, with the ultimate goal of sustaining Moore's Law. Among various studies, some are focused on novel device architecture, while others are exploring methods for improved channel control. In this pursuit, the tunnel FET and the junction-less FET have emerged as promising candidates for low-power applications. In this thesis we have studied the Junction-less nanowire Tunnel Field Effect Transistor (JLN-TFET), which takes the combined advantage of Tunnel Field Effect Transistor (TFET) and junction-less Field Effect transistor (JLFET) by utilizing Channel Engineering and Gate Engineering. Gate Engineering modulates the carrier density in the nanowire channel and creates a tunneling barrier that allows for effective charge transport. Whereas Channel Engineering is used to modify the channel region. The integration of gate engineering and channel engineering was explored with a Hetero-structure device comprising germanium (Ge) and Silicon (Si). A uniform high doping concentration (10-19 cm-3) has been used to make the structure junction-less. The gate work function is set at 4.5 eV while the source work function is 5.93 eV. The optimized gate all around hetero junction less nanowire tunnel field effect transistor (GAA-H-JLNTFET) exhibit notable performance compare to junction less nanowire tunnel FET (JLTFET). Both the structures are compared and analyzed using the extensive TCAD simulation. As an application, the proposed structure was found suitable for the low power biosensor and to check the performance of the biosensor, sensitivity is calculated. The drain current is taken as the sensitivity parameter. The proposed structure GAA-H JLNTFET exhibits the ON current (ION) 6.5x10-5µA/m, the off current (IOFF) measures 5.7x10-18 µA/m, the subthreshold slope (SS) is 12mV/Dec, and ION/IOFF is 1.37x1013 which makes them immune to short channel effect and suitable to low power application in Nano regime. For the simulation and analysis, the Silvaco Atlas 2D simulator is used.